Traditionally, dynamic random access memory (“DRAM”) devices have been architected for “multi-drop” configurations in which signal lines are connected to several signal terminals in parallel. As the operating speed of memory devices continues to increase, this approach fails to provide adequate performance. More recent DRAM device architectures have abandoned the multi-drop approach and are instead architected for point-to-point configurations in which each signal line is connected between only two signal terminals. Point-to-point configurations allow cleaner, more controlled signaling that allows much higher data transfer rates. Point-to-point topologies require low pin count, and high data rates per pin in order to maintain and expand system memory density.
With further increases in the operating speed of memory devices, even point-to-point architectures can become inadequate. In particular, timing skew between command, address and data signals transmitted in parallel in multiple lanes, i.e., buses, can become skewed relative to each other. Further, the timing between these command, address and data signals can become skewed relative to clock signals forwarded along with the command, address and data signals. As a result, it is often necessary to initialize memory systems before they can be used. The circuitry needed to accomplish this initialization in both a host controller and each of several memory devices coupled to either the host controller or another memory device can be highly complex. In a processor-based system having a large number of memory devices, the cost added to the system by including this complex circuitry in the host controller and all of the memory devices can increase the cost of such processor-based systems.
There is therefore a need for an initialization system and method that can, for example, relatively inexpensively initialize a memory system that couples data to and from memory devices through high-speed buses.